1. Field of the Invention
The present invention relates to a method of production of a circuit board, a semiconductor device, and a plating system, more particularly relates to a method of production of a circuit board for mounting a semiconductor chip, a semiconductor device comprised of this circuit board and a semiconductor chip etc. mounted on it, and a plating system able to be used for that method of production.
2. Description of the Related Art
In recent years, three-dimensional mounting structures comprised of a plurality of vertically stacked semiconductor chips have been proposed.
These are comprised for example by mounting a semiconductor chip on a circuit board by flip-chip bonding etc. to obtain a unit component and stacking a plurality of these to obtain a three-dimensional module.
This circuit board is produced by forming interconnects comprised of copper etc. on a glass substrate or silicon substrate.
If the pitch of the bumps of the semiconductor chip mounted by flip-chip bonding on interconnects of the circuit board becomes less than for example 10 μm, the flatness of the surface of the circuit board becomes important. From this viewpoint, the interconnects of a circuit board have been formed by forming holes or grooves in the substrate and burying them with a copper layer etc., that is, the use of the damascene process.
To form interconnects on a substrate by the damascene process, holes or grooves corresponding to the desired interconnect patterns are formed in one surface of the substrate, a plating power supply layer (plating current supply layer) is formed by sputtering, electroless plating, etc., a conductive layer comprised of copper etc. is buried in the holes or grooves by electroplating through this plating power supply layer, then the conductive layer at the portions other than the holes and grooves is removed by polishing, whereby interconnects of the desired patterns comprised of the parts of the conductive layer buried in only the holes or grooves are formed.
In the past, the conductive layer was formed only on one surface of the substrate by electroplating. Further, in the case of electroplating, it is necessary to supply a plating current between a power supply electrode serving as an anodic electrode provided in a plating bath and the plating power supply layer of the substrate serving as the cathodic electrode, so the plating was performed in the state with the power supply electrode fixed to a predetermined position of the plating power supply layer.
In the method of production of a circuit board of the past, however, since the conductive layer was formed on only one surface of the substrate and was not formed on the other surface or the sides of the substrate, the interface between the conductive layer and the underlying plating power supply layer was liable to become exposed at the periphery of the substrate. Further, since the power supply electrode of the plating system was fixed to part of the periphery of the plating power supply layer of the substrate, the conductive layer was not formed at the portion contacted by the power supply electrode. Even near it, the conductive layer was liable to not be formed since the plating current density etc. fluctuated. That is, electroplating did not occur at the portion of the plating power supply layer contacted by the power supply electrode of the substrate or its vicinity, the plating power supply layer was exposed, and as a result the interface between the conductive layer and the plating power supply layer became exposed.
In this way, in the method of production of a circuit board of the past, the interface between the conductive layer and the underlying plating power supply layer was liable to be exposed at the periphery of the substrate or the portion contacted by the power supply electrode or its vicinity. If polishing the conductive layer by for example chemical mechanical polishing (CMP) in this state, there was the problem that the CMP polishing material would invade the interface between the conductive layer and plating power supply layer and thereby cause the conductive layer to peel off and prevent the efficient formation of buried interconnects.